A technique conventionally adopted to align in time two signals (for instance a carrier modulated by an information signal and a local oscillator signal used to demodulate the information signal conveyed on the aforesaid carrier) is the one known by the acronym PLL (Phase Locked Loop). However, this technique, especially in its more sophisticated implementations, is scarcely suitable for use with elementary, or simple, digital circuits, particularly when the circuits are to be manufactured and used in large quantities, with the subsequent need to contain the complexity and costs associated with individual circuits.